The present invention relates to a semiconductor device and, more particularly, to a technique for repairing a defect by substituting a spare memory cell for a defective memory cell. Further, the invention relates to a technique for efficiently storing addresses.
References referred in the specification are as follows.
{REF 1} Japanese patent laid-open No. 8-77791 (counterpart U.S. Pat. No. 5,621,691)
{REF 2} Japanese patent laid-open No. 2-192100 (counterpart U.S. Pat. No. 5,265,055)
{REF 3} U.S. Pat. No. 5,631,862
{REF 4} Japanese patent laid-open No. 4-274096 (counterpart U.S. Pat. No. 5,430,679)
The references will be referred to by the above reference numbers.
The packing density of a semiconductor memory has been increasing and a dynamic random access memory(DRAM) of 64 mega bits is being produced in quantity. When elements are becoming finer and the number of elements is increasing in association with the increase in the packing density, a problem of deterioration in the yield arises. As a countermeasure, there is a so-called a redundancy technique for repairing a defective memory cell by substituting a spare memory cell which is preliminarily provided on a memory chip for the defective memory cell.
In a redundancy circuit, a repairing address of a defective part is stored by nonvolatile storing means. As the nonvolatile storing means, a method of using fuses made of conductive layers and storing a repairing address depending on whether any of the fuses is blown or not with a laser is typical. When an address inputted from the outside in the event of accessing a memory coincides with the repairing address, the redundancy circuit instructs selection of a spare word line or a spare bit line and spare memory cells connected to the selected line are substituted for defective memory cells.
FIGS. 1 and 2 of {REF 1} show an example of the method of storing a defect address by using fuses. {REF 1} discloses a technique such that, in order to replace a column selection line designated by a binary address of eight bits, a repairing address is stored by using total nine fuses, of eight fuses for the binary address and one master fuse.
Prior to the present invention, the inventors of the present invention had examined the relation between the number of fuses in a redundancy circuit of a DRAM having an extremely large capacity such as 256 mega bits or 1 giga bits and the number of fuses blown for programming a defect address in the fuses. The number of fuses in a DRAM as an object is few thousands in total and it was found that enlargement in the chip area with the increase in the number of fuses and increase in time for storing the fuses hinders reduction in the manufacturing costs of a semiconductor device.
According to the result of the examination of the inventors, systems of storing address information by using fuses are mainly divided into two kinds; a system of storing a binary address in a binary address format, and a system of storing a decoded address in a decoded address format obtained by decoding the binary address. In order to distinguish the two systems from each other, in the specification, the former will be called as a binary address programming system (hereinbelow, abbreviated to xe2x80x9cbinary systemxe2x80x9d) and the latter will be called as a decoded address programming system (hereinbelow, abbreviated to xe2x80x9cdecode systemxe2x80x9d). According to the binary system, although the number of fuses decreases, the number of fuses to be programmed increases. On the other hand, according to the decode system, although the number of fuses to be programmed decreases, the number of fuses increases.
In order to quantify the number of fuses in the binary system and the decode system, the inventors made models shown in FIGS. 3 to 6. The example relates to a case that four repairing addresses are stored in an address space expressed by three bits in a binary address and eight bits in a decoded address.
FIG. 3 shows an example of the decode system. In FIG. 3, when four addresses DA0, DA2, DA3, and DA6 in decoded addresses DA0 to DA7 obtained by decoding a 3-bit binary address become high, repair-decision results RH0 to RH3 become high. Four fuse sets DFS0 to DFS3 are provided to store the four repairing addresses. Each fuse set is made up of fuses corresponding to decoded addresses DA0 to DA7 of eight bits. In FIG. 3, the fuse-decision results are schematically shown. Fuses marked with X are blown and logic xe2x80x9c1xe2x80x9d. Other fuses remain logic xe2x80x9c0xe2x80x9d as an initial value. FIG. 4 illustrates an example of a repair decision circuit of the decode system. Address compare circuits DACP0 to DACP3 are provided for the fuse sets DFS0 to DFS3, respectively. The address compare circuits DACP0 to DACP3 generate the repair-decision results RH0 to RH3, respectively, by obtaining the ANDs between the fuse-decision results of the corresponding fuse sets DFS0 to DFS3 and the inputted addresses DA0 to DA7 and obtaining the OR of the ANDs.
FIG. 5 shows an example of the binary system. In FIG. 5, four fuse sets BFS0 to BFS3 are provided to store four repairing addresses. Each fuse set is made up of three fuses corresponding to binary addresses AA0 to AA2 of three bits and one fuse (so-called a master fuse) for storing information USE indicating whether repair is to be made or not. In the binary system, the master fuse is indispensable. FIG. 5 schematically shows fuse decision results such that fuses marked with X are blown and logic xe2x80x9c1xe2x80x9d. FIG. 6 shows an example of a repair decision circuit of the binary system. Address compare circuits BACP0 to BACP3 are provided for the fuse sets BFS0 to BFS3, respectively. The address compare circuits BACP0 to BACP3 generate repair-decision results RH0 to RH3, respectively, by obtaining the exclusive ORs of fuse-decision results of the corresponding fuse sets BFS0 to BFS3 and the addresses AA0 to AA2 to be inputted and obtaining the AND of the exclusive ORs and the fuse-decision result storing the information USE.
The number of fuses required in the two systems will now be generalized. The number NDF of fuses in the decode system necessary to store NS addresses from ND (ND=2{circumflex over ( )}NA) obtained by decoding NA bits of a binary address is as follows.
NDF=NSxc2x7ND=NSxc2x7(2{circumflex over ( )}NA)xe2x80x83xe2x80x83(EQ. 1)
The numerical sign xe2x80x9c{circumflex over ( )}xe2x80x9d denotes the power hereinbelow. In association with the increase in the number NA of addresses, the number NDF of fuses in the decode system remarkably increases. In the example of FIG. 5, NA=3, ND=8, NS=4, and NDF=24.
Meanwhile, the number NBF of fuses required in the binary system is obtained as follows.
NBF=NSxc2x7(NA+1)xe2x80x83xe2x80x83(EQ. 2)
Although the number is smaller than that in the decode system, it still increases with the increase in capacity. Addition of xe2x80x9c1xe2x80x9d in (EQ. 2) is to count the master fuse. In the example of FIG. 3, NA=3, NS=4, and NBF=16.
The area of fuses depends on the accuracy of a laser and scaling equivalent to the lithography technique is difficult to achieve. Consequently, even if the number of fuses is the same, the ratio of the area of fuses on a memory chip becomes higher as the progress of the lithography technique. As the number of fuses increases, the area of them increases. Not only the area of the fuses themselves but also the area of a fuse decision circuit and an address compare circuit also increases as the number of fuses increases. Especially, since the exclusive OR is used in the binary system, the circuit scale is accordingly enlarged. Due to the above, the overhead of the repair decision circuit to the chip area increases.
In the decode system, since the number of fuse to be programmed in one fuse set is always one, the programming is easily made but the number of fuses for storing one defect address is relatively large. On the other hand, in the binary system, although the number of necessary fuses is smaller than that in the decode system, the number of fuses to be blown is large. In case of the address of a defect is 111 in binary number, it is necessary to program total four fuses consisting of three fuses corresponding to the binary address 111 and one master fuse. Accordingly, the time to blow the fuses increases, the number of laser repair equipment required to fabricate semiconductor memories in quantity increases, and the throughput deteriorates. As the number of fuses to be blown increases, the probability of occurrence of a defect in the fuses during the blowing process becomes high and it affects on the yield.
It is an object of the invention to realize a semiconductor memory device having a redundancy circuit which solves the problems. More specifically, it is an object to realize a redundancy circuit having a smaller area and a higher repairing efficiency and whose programming time required to store a repairing address is short.
According to the invention, in order to achieve the object, there is provided a semiconductor device comprising a plurality of memory circuits designated by ND (ND=2{circumflex over ( )}NA) addresses expressed by a binary address of NA bits and a defect address storing circuit including ND storage elements for storing NS (two or more) defect addresses of two in relation to a plurality of defects in the plurality of memory circuits, wherein the NS defect addresses are addresses which are selected from the ND addresses and are different from each other and each of the ND storage elements stores a first logical state or a second logical state in one bit.